The need to maintain "cache coherence" in multiprocessor systems is well known. Maintaining "cache coherence" means, at a minimum, that whenever data is written into a specified location in a shared address space by one processor, the caches for any other processors which store data for the same address location are either invalidated, or updated with the new data.
There are two primary system architectures used for maintaining cache coherence. One, herein called the cache snoop architecture, requires that each data processor's cache include logic for monitoring a shared address bus and various control lines so as to detect when data in shared memory is being overwritten with new data, determining whether it's data processor's cache contains an entry for the same memory location, and updating its cache contents and/or the corresponding cache tag when data stored in the cache is invalidated by another processor. Thus, in the cache snoop architecture, every data processor is responsible for maintaining its own cache in a state that is consistent with the state of the other caches.
In a second cache coherence architecture, herein called the memory reference architecture, main memory includes a set of status bits for every block of data that indicate which data processors, if any, have the data block stored in cache. The main memory's status bits may store additional information, such as which processor is considered to be the "owner" of the data block if the cache coherence architecture requires storage of such information.
The present invention utilizes a different cache in which each data processor that has a cache memory maintains a master cache index and a system controller maintains a duplicate cache index for each such cache memory. For each memory transaction by a data processor in which there is a cache miss or other state change requiring communication with either main memory or other cache memories in order to maintain cache coherence, the System Controller does a cache index lookup on all the duplicate cache lookups, the system controller selects the sequence of actions needed to perform the memory transaction.
In prior art "snoop bus" cache coherence systems, it is impossible for two overlapping memory transactions to simultaneously access the same address because only one cache coherent memory transaction can be performed at a time, and that transaction is broadcast to all data processors so that they can "snoop" on the address and control busses and thereby keep their local cache memories consistent with memory transactions performed by other data processors.
In prior art memory reference architecture cache coherent systems it is also impossible for two overlapping memory transactions to simultaneously access the same address because the memory reference logic inherently serializes such memory transactions.
In the "duplicate cache tag" architecture of the present invention in which multiple data processors can initiate memory transactions and in which the interconnect can process multiple memory transactions simultaneously, there needs to be a mechanism to avoid "coherence hazards." In particular, the pipelined execution of transactions in the present invention results in multiple transactions being active simultaneously in the System Controller. This would lead to coherence hazards in the system if multiple active transactions shared the same cache index in the Dtags. To avoid such hazards, the System Controller utilizes special transaction activation logic that blocks a first memory transaction from becoming active if a second memory transaction that is already active is using the same cache index as would be used by the first memory transaction. One important exception to this transaction activation blocking is that writeback transactions do not need to be blocked and do not cause other transactions to be blocked.